Advancing Quantum Error Correction With Dual-Rail Technology
D-Wave's peer-reviewed Nature paper demonstrates a fast, high-fidelity two-qubit entangling gate that preserves the error-correction advantages of its superconducting dual-rail qubit architecture. This breakthrough advances the path to practical, fault-tolerant quantum computing.
Removing a Barrier to Fault-Tolerant Quantum Computing
Error correction is one of the industry’s most consequential challenges on the path to scaled fault-tolerant gate-model quantum computing. The benefits of quantum error correction typically come with high overhead in the number of physical qubits, creating substantial engineering complexity, cost and performance constraints.
D-Wave's Nature paper, “An entangling gate for dual-rail erasure qubits,” details a new two-qubit entangling gate, a fundamental building block of quantum computation, designed to support efficient quantum error correction. The research demonstrates approximately 99.9% fidelity during two-qubit operations, with fast gate times of about 500 nanoseconds, enabled by native hardware-level error detection.
The results establish an important foundation for scalable quantum error correction, validating that D-Wave's superconducting dual-rail architecture can reduce the quantum and classical hardware overhead typically required to detect and correct quantum errors while maintaining fast, high-fidelity operations.
D-Wave's dual-rail qubits are superconducting quantum devices that create, store, and manipulate quantum information to perform computations. Unlike other quantum computing architectures, the dual-rail qubit is designed to detect errors at the hardware level. Click here to see the full annotated graphic.
A Two-Qubit Gate Designed for Quantum Error Correction
D-Wave's dual-rail architecture is designed to create a favorable error hierarchy in which the most common quantum errors are also the easiest to correct. The newly published research demonstrates that this favorable error hierarchy is preserved during two-qubit operations, with the technology maintaining both speed and high fidelity. The results establish an important foundation for scalable quantum error correction with substantially lower hardware overhead.
Leveraging these results, D-Wave simulations indicate its dual-rail architecture could reduce the logical error rate by as much as a factor of 10 for each increment in error correction, significantly reducing the physical qubit overhead required for fault-tolerant quantum computing.
The research supports D-Wave's recently announced gate-model development roadmap, which targets a 2032 completion of a 100-logical-qubit system capable of successfully performing more than 1 million operations.
The Hardware
D-Wave’s superconducting dual-rail qubit architecture is designed to make the most common errors the easiset to correct.
The Performance
The research demonstrates approximately 99.9% fidelity during two-qubit operations with gate times of about 500 nanoseconds.
The Impact
Dual-rail architecture combines fast superconducting operations with high-fidelity performance while preserving the native hardware-level error hierarchy.
“Building a fault-tolerant quantum computer requires systematically solving a series of difficult scientific and engineering challenges, with each success bringing us closer to a scalable system. This research demonstrates one of the foundational capabilities of our dual-rail architecture and we believe it brings us an important step closer to fault-tolerant gate-model quantum computing.”
Dr. Trevor Lanting
Chief Development Officer at D-Wave
The Era of Error-Aware Quantum Development
The hardware-level error detection capabilities validated in the Nature paper are expected to give researchers new ways to explore error-aware algorithms and quantum error correction. D-Wave's forthcoming gate-model quantum simulator will provide developers with new tools and data to better understand quantum behavior, prototype quantum applications and error-correction routines, and explore advanced workflows.
Gate-Model Quantum Computing
Explore D-Wave’s superconducting dual-rail architecture, built-in error detection, error-aware programming capabilities and gate-model roadmap.
Why Error Awareness Matters
Learn why visibility into errors during computation matters for error-aware algorithm development and more efficient quantum error correction.
Gate-Model Simulator Data Sheet
Explore how D-Wave's forthcoming gate-model quantum simulator is designed to prototype, test, and validate novel error aware applications and error correction routines before execution on quantum hardware.