Why Error Awareness Matters: A Faster Path to Fault-Tolerant Quantum Computing

For much of the quantum computing industry's history, progress has been measured by physical qubit count. But as the field matures, it is increasingly clear that qubit count alone will not determine who delivers commercially viable, fault tolerant gate-model quantum computers first. 

What really matters is a system's ability to execute operations reliably, efficiently, and at scale.

That principle is at the heart of D-Wave's gate-model roadmap. D-Wave is pursuing a path to commercial fault-tolerant quantum computing with a goal of delivering 100 logical qubits capable of successfully performing more than one million operations by 2032. 

Our approach brings together several core capabilities: superconducting dual-rail qubits with built-in error detection, on-chip cryogenic control technology, deep expertise in scaling superconducting quantum systems, and an enterprise-grade quantum cloud infrastructure. 

D-Wave's gate-model roadmap targets 100 logical qubits capable of successfully performing more than one million operations by 2032.

Together, these technologies give D-Wave a differentiated path toward the performance, efficiency, and scalability required to make commercial gate-model quantum practical. 

To help developers start preparing for that future now, we recently announced our forthcoming gate-model quantum computing simulator. Expected to be the first-of-its-kind built for error-aware programming, the simulator is built around the dual-rail architecture that underpins our gate-model roadmap. It is intended to provide visibility into error-detection data so developers can prototype applications, develop error correction techniques, and build error-aware programming expertise they can carry forward as the roadmap advances. 

Once available through D-Wave's Leap™ cloud platform, the simulator is expected to support up to 21 qubits and include both ideal and hardware-emulation modes, Monte Carlo simulation of real-time quantum system dynamics, and integration with D-Wave's Ocean™ SDK. 

Customers can sign up here to request future access to our forthcoming gate-model quantum simulator and systems.

Why Fault-Tolerant Quantum Computing Needs a Different Approach

Fault-tolerant gate-model quantum computing is expected to unlock transformative applications in areas such as quantum chemistry, materials science, and AI. But successfully developing those applications will require quantum systems that can manage errors efficiently while maintaining the speed and scalability necessary for practical computing. 

Today, many quantum computing architectures face a fundamental tradeoff. Trapped-ion and neutral-atom systems can achieve high qubit fidelities, but their operations are relatively slow. Superconducting systems offer dramatically faster operation speeds, but reducing error-correction overhead while maintaining high performance remains a significant challenge. Commercially viable quantum computers will need to perform computations quickly while correcting errors efficiently enough to scale to increasingly complex workloads. 

D-Wave's gate-model roadmap can address that challenge by combining efficient error correction, fast gate speeds, and a scalable superconducting architecture. 

How D-Wave's Dual-Rail Qubits and On-Chip Cryogenic Control Are Expected to Accelerate the Path to Fault Tolerance

D-Wave’s superconducting dual-rail architecture embeds error detection directly into the qubit design, making errors observable as they occur during computation. This built-in error awareness can identify approximately 90% of errors in real-time, dramatically reducing the physical resources required for quantum error correction. 

That matters because error correction is one of the largest barriers to useful fault-tolerant quantum computing. The more efficiently a system can detect and manage errors, the fewer physical qubits and operations may be required to produce reliable logical qubits. In other words, error awareness can directly improve the economics, scalability, and practicality of fault-tolerant quantum computing.  

With error detection, D-Wave has demonstrated 99.9% two-qubit fidelities, corresponding to physical error rates of roughly one error per 1,000 operations. By combining these fidelities with the fast operation speeds of superconducting circuits, D-Wave expects its dual-rail approach to enable quantum error-correction cycles running 100 to 1,000 times faster than those of neutral-atom or trapped-ion systems. 

Another important metric is Lambda, which measures how rapidly a quantum computer’s errors are reduced as more error-correction capability is added. A higher Lambda means errors fall faster, requiring fewer physical resources to reach useful fault-tolerant performance.  

D-Wave’s roadmap targets a Lambda of 10, which we expect will reduce errors by a factor of 10 for each increment in error correction. For comparison, the broader quantum computing industry has demonstrated Lambda values of about 2, meaning that each additional increment of error correction reduces errors by about half. We believe that Lambda should become a key metric for measuring progress toward fault-tolerant quantum computing because it directly reflects how efficiently a system can turn physical qubits into reliable logical qubits. 

 Equally important is the ability to efficiently control qubits at scale.  D-Wave's proprietary on-chip cryogenic control technology, announced earlier this year, significantly reduces the wiring required to control large numbers of qubits, without degrading qubit fidelity. Without this technology, useful gate-model systems would require an impractically large amount of physical infrastructure. 

A Practical Path to Commercial Gate-Model Quantum Computing

The race to fault-tolerant gate-model quantum computing will not be won simply by building physically larger systems. It will be won by combining speed, scalability, and efficient error correction in a way that enables useful applications.  

D-Wave’s approach is differentiated by its focus on error awareness from the qubit level up. By making errors visible as they occur, our dual-rail architecture is designed to reduce correction overhead and improve the efficiency of the path to reliable logical qubits. Combined with fast superconducting gate speeds, on-chip cryogenic control, and decades of experience scaling superconducting quantum systems, we believe this gives D-Wave a compelling path toward scalable, commercial gate-model quantum computing.  

With the introduction of our forthcoming gate-model simulator, we are also giving developers an opportunity to begin preparing for that future today. By learning to program with error awareness now, customers can build expertise that may become increasingly valuable as fault-tolerant quantum systems advance from roadmap to reality.